The invention relates generally to a semiconductor device and, more particularly, to a method for forming a fine pattern by a spacer patterning technology.
As the sizes of circuit patterns constituting semiconductor devices decrease, there occurs a limitation in an optical resolution in an exposure process that transcribes the pattern onto a wafer. A Spacer Patterning Technology (SPT) has been introduced as a method for overcoming the limitation in the optical resolution and forming finer patterns. In SPT, a spacer is formed on a wafer and an etch target layer under the spacer is selectively patterned using the spacer as an etch mask, thereby forming a fine pattern having a line width determined as a function of the thickness of the spacer. This SPT is expected to overcome the resolution limitation in ArF exposure equipment and thus to be useful to realize a fine pattern having a line width of 40 nm on a wafer.
In SPT, the spacer is formed by a spacer etch with respect to a layer for the spacer. In order to divide the spacers from the spacer layer, the spacer layer is deposited so as to cover a sacrificial pattern or a partition. The spacer etch that is an anisotropic etch is performed on the spacer layer to form the spacers attached to the both side walls of the partition. Therefore, a process for patterning the partitions is primarily required to form the spacer.
To pattern these partitions, a photoresist layer is applied onto a partition layer and a layout of the partition is exposed and transcribed onto the photoresist layer. Thereafter, the exposed photoresist layer is developed to form a photoresist pattern. However, since the ArF light source used to the exposure has quite a short frequency, there is a limitation in a thickness of the photoresist layer capable that can realize the pattern from the result of accurate exposure and development. Since there is a limitation in the ability to increase the thickness of the photoresist pattern, there is also a limitation in a thickness of the partition layer patternable by a selective etch process using this photoresist pattern. Since there is a limitation in the ability to increase the thickness of the partition layer, it is also difficult to ensure that the partition patterned from this partition layer has a required, sufficiently high height.
The limitation to the height of the partition ultimately leads to a limitation to a height of the spacer, and the limitation to the height of the spacer result in a limitation to a thickness of a under layer to be patterned by a selective etch performed using the spacer as an etch mask. Since a height of a circuit pattern such as a gate required on a wafer may be hundreds to thousands angstroms, it is difficult to directly use the spacer having a low height, that can only be formed in a limited height, as an etch mask required to selectively etch a layer for the gate.
To overcome this difficulty, a hard mask capable of realizing a higher etch selectivity to a pattern target layer is introduced. Layers for the hard mask are introduced as a multilayer stack into a lower side of the spacer so that the hard mask can have a sufficient height and can be accurately transcribed with a shape of the pattern from the spacer having relatively low height. An upper layer introduced into relatively upper side of the multilayer stack acts as a sub mask for etching the lower layer, thereby more accurately transcribing the shape of the spacer onto the lower-most layer. In the case of introducing the hard mask of the multilayer stack as described above, thicknesses and stacking order of the layers constituting the stack are determined in consideration of extents of realization of the etch selectivities among the layers.
As described above, the layer for the hard mask is introduced as a stack structure having a large number of layers and a partition layer for attaching the spacer is further stacked on the hard mask stack. Therefore, the entire stack for the spacer patterning has a relatively large number of stacked layers. Accordingly, an excessive thermal stress is caused in the lower layer due to high thermal requirements in a process of depositing the upper layer, and this may result in a lifting phenomenon in the lower layer. This lifting phenomenon due to the thermal stress may be resulted from that layers having different materials are stacked with interfaces therebetween for realizing significant etch selectivities between the layers and thus an interface properties or an adhesive properties becomes weak.
Therefore, it is necessary to exclude the layer having relatively high thermal requirements when depositing the upper layer of the stack. Also, as it is necessary to stack and selectively etch a plurality of layers, an entire process of the SPT becomes very complicated and a process cost is increased. Accordingly, it is necessary to develop a method capable of realizing stacking of layers for the hard mask and the partition through a combination of fewer layers and realizing a stack structure that is relatively stable to the thermal stress.